1. Field of the Invention
The invention relates to data processing systems and more particularly to a method and apparatus for looking ahead in the instruction stream of a microprocessor for a branch instruction and for calculating the target address of the branch.
2. Description of the Related Art
The above referenced copending application Ser. No. 07/630,499 describes a Reduced Instruction Set Computer (RISC) that is a superscaler pipelined microprocessor wherein multiple functions are performed during each pipeline stage.
An Instruction Cache supplies an instruction sequencer with at least three instruction words per clock. The Instruction Sequencer decodes incoming instruction words from the Cache, and issues up to three instructions on a REG interface, a MEM interface and/or a branch logic within the Instruction Sequencer. The instruction sequencer includes means for detecting dependencies between the instructions being issued to thereby prevent collisions between instructions.
The above referenced copending application Ser. No. 07/630,535 describes an instruction sequencer that controls instruction execution by issuing Micro Addresses (UA)s each cycle, decides which instruction should be executed in the next cycle and handles Instruction pointer (IP) bookkeeping by gathering many boundary conditions from other units, makes guesses and then issues an instruction pointer in such a way that a preceding instruction will not see the change and the following instruction will, taking into account instruction pipelining, branch prediction and fail recovery, macro flow instruction lookahead, and other inter-dependent mechanisms.
A conditional branch instruction is a departure from the normal sequence of executing instructions that occurs if specified criteria are met. The branch is the set of instructions that are then executed up to the point that a decision instruction in the branch returns the execution to the instruction stream that was executing before the branch was taken.
It is an object of the present invention to provide a branch lookahead adder that will hide the execution time of a branch instruction by looking ahead in the instruction stream for branch instructions and then calculating the branch address.